This invention relates to systems, methods and computer program products for designing, testing and fabricating integrated circuits, and more particularly to systems, methods and computer program products for determining a density of a pattern in an integrated circuit and for simulating a chemical-mechanical polishing process using the density that was determined.
Present-day Ultra-Large Scale Integration (ULSI) integrated circuits may include hundreds, thousands or millions of interconnected active and passive electronic devices in an integrated circuit chip. The large capital investment to fabricate and test these ULSI circuits prior to sale, and the difficulty, expense and/or loss of goodwill associated with reworking and replacing integrated circuits that fail to operate as planned, have increased the need to accurately simulate the design and fabrication of integrated circuits prior to their fabrication.
In fabricating integrated circuit devices, a plurality of patterned layers, such as wiring layers, generally are formed on a wafer. The patterned layer may cause a relative height difference, often referred to as a step difference, between the patterned and non-patterned areas of the layer. This step difference may increase with the number of layers that are formed, the fineness of the pattern and/or the increase in the level of integration. As is well known to those having skill in the art, an increased step difference can cause failure in many individual integrated circuit fabrication steps, and may also degrade the operating characteristics of the integrated circuit. Accordingly, it is known to provide planarization technology to reduce and preferably minimize the step differences that occur during fabrication of an integrated circuit. Chemical-mechanical polishing (CMP) is a widely used planarization technology.
CMP may be carried out using an apparatus such as that shown in FIG. 1 to planarize integrated circuits as shown in FIGS. 2A and 2B. Referring to FIG. 1, a wafer containing integrated circuits to be planarized is mounted on a wafer carrier 150. As shown in FIG. 2A, the wafer may include an integrated circuit substrate 210 on which a patterned layer 220, such as a metal wiring layer is formed. A planarization layer 230 is formed on the patterned layer 220. In order to perform the CMP process, the wafer carrier 150 is rotated about an axis 160, while a platen 120 on which a polishing pad 110 is mounted, also is rotated about an axis 130. A polishing slurry 170 is disposed on the polishing pad 110, so that the wafer 140 is exposed to a chemical polishing process, in addition to the mechanical polishing due to the friction between the polishing pad 110 and the wafer 140. By performing CMP for a predetermined period of time, the thickness of the planarization layer 230 of FIG. 2A may be reduced, resulting in a polished planarization layer 235, as shown in FIG. 2B, that is generally more planar than the initial planarization layer 230 of FIG. 2A.
Unfortunately, the results of a CMP process may vary depending on several parameters including polishing time, velocity of the platen 120, velocity of the wafer carrier 150, downward polishing pressure of the wafer 140 on the polishing pad 110, and/or the elastic modulus of the polishing pad 110. Accordingly, in certain cases, the CMP may cause a dishing phenomenon (portion A of FIG. 2B) to occur where a region of the planarization layer 235 without a pattern is depressed, or may cause a thinning phenomenon (portion B of FIG. 2B) to occur where fine patterns are polished by the CMP. Accordingly, it is desirable to improve and preferably optimize the above-parameters, to reduce and preferably minimize dishing and/or thinning. Unfortunately, the optimization of these parameters may be a difficult and time consuming task, which may require numerous test runs of the CMP process.
Thus, in order to reduce the time and/or labor involved in determining the parameters through multiple CMP test trials, analytical modeling or simulation using computers has been devised. However, such analytical modeling or simulation should provide accurate prediction within a reasonable time.
U.S. Pat. No. 5,552,996 to Hoffman et al. describes a method and system that can facilitate the control of an IC chip fabrication level of an IC chip fabrication process based upon the design pattern of the IC chip being fabricated. A grid having multiple sections is imposed over the design pattern of a fabrication level of the IC chip. Then, pattern density values are automatically established for the design pattern contained in each section of the grid. The IC chip fabrication level is then controlled based upon the pattern density values. For example, the established pattern density values facilitate the automatic determination of a CMP process stop parameter, or the automatic compensation for etch rate variations caused by pattern density differences across the design pattern of the IC chip.
Moreover, a publication by Takahashi et al. entitled Modeling of Chemical Mechanical Polishing Process for Three-Dimensional Simulation, 1997 Symposium on VLSI Technology, June 1997, pp. 25-26, describes a new model of CMP planarization. Machine time of actual calculation can be estimated less than {fraction (1/100)} of Finite Element Method and the simulation is in excellent agreement with experimental results. This model provides a physical image of planarization for three-dimensional surface profile during CMP. Furthermore, an optimized LSI chip layout or an appropriate processing condition can be estimated. In particular, this method can incorporate the data from adjacent meshes that surround a specified mesh.
Notwithstanding the above discussion, there continues to be a need for systems, methods and/or computer program products that can accurately simulate CMP results. Moreover, conventional simulators may carry out simulations on an integrated circuit chip level of a wafer, rather than over the entire wafer. Because tens or more of integrated circuit chips are repeatedly fabricated with the same pattern in a wafer, the CMP results over the entire wafer may be predicted based on the CMP results with respect to only one chip. However, wafers may be asymmetric due to a flat zone thereof, and/or the different patterns that may exist at the wafer periphery, where integrated circuits are not found.
Embodiments of the present invention can provide systems, methods and/or computer program products that can obtain an effective pattern density of a layer of an integrated circuit from layout data that defines the layout. A grid of pattern cells is defined for the layout data. A respective pattern density is determined for a respective pattern cell in the grid. An effective pattern density is calculated for a first pattern cell in the grid. The effective pattern density for the first pattern cell is a function of the pattern density of at least a second pattern cell in the grid that is remote from (i.e. nonadjacent) the first pattern cell, and a distance of the at least a second pattern cell from the first pattern cell. Adjacent cells also may be included and preferably are included, in the effective pattern density.
In other embodiments, a weighted average pattern density of a plurality of pattern cells in the grid around the first pattern cell and including the second pattern cell is calculated, that is inversely weighted as a function of the respective distances of the plurality of pattern cells from the first pattern cell. In yet other embodiments, the respective patterned densities of the respective plurality of pattern cells is multiplied by a weighted value that is inversely proportional to respective distances of the plurality of pattern cells from the first pattern cell and by the pattern density of the first pattern cell, to obtain a respective weighted pattern density for a respective one of the plurality of pattern cells. The respective weighted pattern densities are summed and divided by the number of cells in the selected plurality of pattern cells, to obtain the effective pattern density of the first pattern cell.
In still other embodiments, the pattern densities may be scaled as a function of fabrication processes that are used to fabricate the integrated circuit. Scaling may be performed by changing a pattern width and/or by multiplying a pattern density by a scaling factor based on the fabrication processes that are used to fabricate the integrated circuit.
Other embodiments of the present invention can determine the thickness of the planarization layer as a function of CMP polishing time, based on the effective pattern density. Moreover, in determining the thickness of the planarization layer as a function of CMP polishing time, at least one of the parameters may vary as a function of location of the integrated circuit in the wafer. These parameters therefore may be determined as a function of the location of the integrated circuit in the wafer.
According to yet other embodiments of systems, methods and/or computer program products according to the present invention, a layout which defines a pattern of the patterned layer is divided into a plurality of pattern cells. A percentage of the pattern occupying area in each pattern cell is computed as the pattern density of each pattern cell. Then, the effects of patterns of peripheral pattern cells on the pattern density of a selected cell are computed, for each of the pattern cells, as a function of the distances of respective peripheral cells from the selected pattern cell, to obtain an effective pattern density for each of the pattern cells based on the computed distances. When CMP is performed on a planarization layer, stacked on the patterned layer, the thickness and/or the step difference distribution of the planarization layer in the integrated circuit in accordance with the polishing time are computed based on the effective pattern density of each pattern cell in which the effects of patterns of the peripheral pattern cells has been reflected.
In yet other embodiments, a pattern may be extended and/or reduced based on the fabrication process that is used for the planarization layer. Accordingly, scaling may be used to evenly extend and/or reduce the pattern prior to computing the pattern density of each pattern cell, or multiplying the pattern density of each pattern cell by a predetermined scaling factor after computing the pattern density of each pattern cell.
In still other embodiments, the thickness and/or the step difference distribution of a planarization layer, which has been computed by an integrated circuit chip level simulation, can be extended to across an entire wafer that includes a plurality of integrated circuit chips. In one embodiment, the relative velocity V of the wafer with respect to a polishing pad, and the pressure P of the polishing pad on the wafer, which can vary in accordance with the position of each chip in the wafer, are computed. The computed parameters are then substituted into an equation used to calculate the thickness of a planarization layer in a chip, so that the thickness and/or the step difference distribution of the planarization layer in each chip of the wafer can be calculated with respect to the positions of each chip within the wafer.
In yet other embodiments, a CMP stop time and/or a monitoring point can be determined, based on the thickness and the step difference distribution of the planarization layer, which have been computed at a chip and/or wafer level. Alternatively, a dummy pattern for compensation of the step difference can be established, so that the results of the simulation can be reflected in the design of the integrated circuit.
Accordingly, the thickness of a planarization layer after CMP can be predicted accurately by using a pattern density which has been calculated in consideration of the effects of patterns of the remote (nonadjacent) pattern cells, and also preferably adjacent pattern cells, as a function of the distances between each cell and the remote pattern cells. Also, the CMP simulation performed at a chip level can be extended to a wafer level.